Phase Noise and Tuning Speed Optimization of a 5-500 MHz Hybrid DDS-PLL Synthesizer with milli Hertz Resolution

Recent research on frequency synthesis concentrates mainly on specific wireless applications requiring high-purity gigahertz carriers in a narrow frequency band, with moderate resolution an tuning speed. A low power consumption is often a must for mobility, thus a PLL solution is indicated. The main benefits of direct digital synthesis (DDS), very wide band operation with millihertz resolution, are more useful for instrumentation, where the higher power consumption is less problematic. A hybrid DDS-PLL approach can preserve most of the DDS benefits, and counter the DDS frequency limitation. This paper emphasizes on phase noise and tuning speed optimization of such an architecture. The implemented synthesizer shows a 5500 MHz output frequency range with millihertz resolution. The single sideband phase noise at 1 kHz offset measures less than –80 dBc/Hz over the full frequency range. Key-Words: Phase Noise, Phase Locked Loop, Direct Digital Synthesis